The present invention is related to a digital Delay-Locked Loop (DLL), and more specifically to an improved version of the adjustable delay portion of the DLL typically found in such circuits.
Purely digital adjustable delay lines are typically controlled by counter-type circuits. If these delay lines adjust the delay based on temperature and/or voltage changes, they can exhibit glitches or possibly even run out of adjustable range if the delay line has been divided into course versus fine segments. Analog delay lines handle the adjustments better, but are known to have more issues with jitter as the delay is never actually stable, but rather constantly adjusting. This is especially true if the analog delay line has to be biased in such a way that large adjustments are to be required after initial lock due to expected temperature changes.
Referring now to FIG. 1, a typical DLL 100 is shown including an adjustable delay line 102 for receiving a CLK clock input and for providing a delayed, locked clock signal at an OUTPUT output node. A fixed delay block 104 is coupled between the output of the adjustable delay line 102 and node 108. A phase detect circuit 106 receives the CLK signal at a first input node, and the delay CLK signal at a second input node. The first and second input nodes of the phase detect circuit 106 are shown receiving respect clock pulses A and C, which is explained further below with respect to FIG. 2. The output of the phase detect circuit 106 is coupled to a control input of the adjustable delay line 102.
Referring now to FIG. 2, a timing diagram is shown including the two signal waveforms corresponding to the input CLK signal, and the delayed CLK signal at node 108. Note in FIG. 2 that the leading edge of the “C” CLK pulse is locked to the leading edge of the “A” pulse of the delayed CLK signal at node 108.
What is desired, therefore, is an improved adjustable delay line suitable for use in a DLL of the type shown in FIG. 1 that does not have the problems associated with prior art digital and analog delay lines described above.